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LTC4447 1 4447f integrated schottky diode 4v to 6.5v v cc operating voltage 38v maximum input supply voltage adaptive shoot-through protection rail-to-rail output drivers 3.2a peak pull-up current 4.5a peak pull-down current 8ns tg risetime driving 3000pf load 7ns tg falltime driving 3000pf load separate supply to match pwm controller drives dual n-channel mosfets undervoltage lockout low pro? le (0.75mm) 3mm 3mm dfn package typical application features applications description high speed synchronous n-channel mosfet driver the ltc ? 4447 is a high frequency gate driver with integrat- ed bootstrap schottky diode that is designed to drive two n-channel mosfets in a synchronous dc/dc converter. the powerful rail-to-rail driver capability reduces switching losses in mosfets with high gate capacitance. the LTC4447 features a separate supply for the input logic to match the signal swing of the controller ic. if the input signal is not being driven, the LTC4447 activates a shut- down mode that turns off both external mosfets. the input logic signal is internally level-shifted to the bootstrapped supply, which functions at up to 42v above ground. the schottky diode required for the bootstrapped supply is integrated to simplify layout and reduce parts count. the LTC4447 contains undervoltage lockout circuits on both the driver and logic supplies that turn off the external mosfets when an undervoltage condition is present. an adaptive shoot-through protection feature is also built-in to prevent the power loss resulting from mosfet cross- conduction current. the LTC4447 is available in the 3mm 3mm dfn package. synchronous buck converter driver distributed power architectures high density power modules , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. LTC4447 driving 3000pf capacitive loads tg boost v in to 38v gnd ts v logic v cc LTC4447 bg pwm v cc 4v to 6.5v in v out 4447 ta01a top gate (tg - ts) 5v/div input (in) 5v/div 4447 ta01b bottom gate (bg) 5v/div 10ns/div
LTC4447 2 4447f electrical characteristics absolute maximum ratings supply voltage v logic ...................................................... ?0.3v to 7v v cc ........................................................... ?0.3v to 7v boost ? ts ............................................. ?0.3v to 7v boost voltage .......................................... ?0.3v to 42v boost ? v cc ............................................................38v ts + v cc ....................................................................42v in voltage .................................................... ?0.3v to 7v driver output tg (with respect to ts) ......... ?0.3v to 7v driver output bg .......................................... ?0.3v to 7v operating temperature range (note 2).... ?40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ................... ?65c to 150c (note 1) symbol parameter conditions min typ max units logic supply (v logic ) v logic operating range 3 6.5 v i vlogic dc supply current in = floating 730 900 a uvlo undervoltage lockout threshold v logic rising v logic falling hysteresis o o 2.5 2.4 2.75 2.65 100 3 2.9 v v mv gate driver supply (v cc ) v cc operating range 4 6.5 v i vcc dc supply current in = floating 600 800 a uvlo undervoltage lockout threshold v cc rising v cc falling hysteresis o o 2.75 2.60 3.20 3.04 160 3.65 3.50 v v mv v d schottky diode forward voltage i d = 10ma i d = 100ma 0.38 0.48 v v the o denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v logic = 5v, v ts = gnd = 0v, unless otherwise noted. pin configuration top view 13 ddma package 12-lead (3mm 3mm) plastic dfn nc nc tg ts bg gnd boost boost boost v cc v logic in 1 2 3 4 5 6 12 11 10 9 8 7
LTC4447 3 4447f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC4447i is guaranteed to meet speci? cations from C40c to 85c. the LTC4447e is guaranteed to meet speci? cations from 0c to 85c with speci? cations over the C40c to 85c temperature range assured by design, characterization and correlation with statistical process controls. electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = v logic = 5v, v ts = gnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units input signal (in) v ih(tg) tg turn-on input threshold v logic 5v, in rising v logic = 3.3v, in rising 3 1.9 3.5 2.2 4 2.6 v v v il(tg) tg turn-off input threshold v logic 5v, in falling v logic = 3.3v, in falling 2.75 1.8 3.25 2.09 3.75 2.5 v v v ih(bg) bg turn-on input threshold v logic 5v, in falling v logic = 3.3v, in falling 0.8 0.8 1.25 1.1 1.6 1.4 v v v il(bg) bg turn-off input theshold v logic 5v, in rising v logic = 3.3v, in rising 1.05 0.9 1.5 1.21 1.85 1.5 v v i in(sd) maximum current into or out of in in shutdown mode v logic 5v, in floating v logic = 3.3v, in floating 150 75 300 150 a a high side gate driver output (tg) v oh(tg) tg high output voltage i tg = C100ma, v oh(tg) = v boost C v tg 140 mv v ol(tg) tg low output voltage i tg = 100ma, v ol(tg) = v tg C v ts 80 mv i pu(tg) tg peak pull-up current 23.2 a i pd(tg) tg peak pull-down current 1.5 2.4 a low side gate driver output (bg) v oh(bg) bg high output voltage i bg = C100ma, v oh(bg) = v cc C v bg 100 mv v ol(bg) bg low output voltage i bg = 100ma 100 mv i pu(bg) bg peak pull-up current 23.2 a i pd(bg) bg peak pull-down current 34.5 a switching time t plh(tg) bg low to tg high propagation delay 14 ns t phl(tg) in low totg low propagation delay 13 ns t plh(bg) tg low to bg high propagation delay 13 ns t phl(bg) in high to bg low propagation delay 11 ns t r(tg) tg output risetime 10% to 90%, c l = 3nf 8 ns t f(tg) tg output falltime 10% to 90%, c l = 3nf 7 ns t r(bg) bg output risetime 10% to 90%, c l = 3nf 7 ns t f(bg) bg output falltime 10% to 90%, c l = 3nf 4 ns t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (pd ? 43c/w) note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability.
LTC4447 4 4447f typical performance characteristics input thresholds vs v logic supply voltage input thresholds for v logic = 3.3v vs temperature bg or tg input threshold hysteresis vs v logic supply voltage v logic undervoltage lockout thresholds vs temperature undervoltage lockout threshold hysteresis vs temperature input thresholds for v logic 5v vs temperature quiescent supply current vs supply voltage v cc undervoltage lockout thresholds vs temperature bg or tg input threshold hysteresis vs temperature v logic supply (v) 3.0 3.5 0 input threshold (v) 1.0 4.0 4.0 5.0 5.5 4447 g01 0.5 2.0 2.5 3.0 3.5 1.5 4.5 6.0 6.5 v ih(tg) v il(tg) v il(bg) v ih(bg) temperature (c) input threshold (v) 1.0 2.0 3.0 0.5 1.5 2.5 C10 20 50 80 4447 g02 110 C40 v ih(tg) v logic = 3.3v v il(tg) v il(bg) v ih(bg) temperature (c) input threshold (v) 3 4 5 4447 g03 2 1 0 C10 C40 110 20 50 80 v ih(tg) v logic 5v v il(tg) v il(bg) v ih(bg) v logic supply (v) 3.0 3.5 0 bg or tg input threshold hysteresis (v) 0.10 0.35 4.0 5.0 5.5 4447 g04 0.05 0.20 0.25 0.30 0.15 4.5 6.0 6.5 temperature (c) bg or tg input threshold hysteresis (v) 0.25 0.30 0.35 4447 g05 0.15 0 C40 C10 20 50 80 110 0.40 0.20 0.10 0.05 v logic = 5v v logic = 3.3v supply voltage (v) 3.0 0 supply current (ma) 0.1 0.3 0.4 0.5 1.0 0.7 4.0 5.0 5.5 4447 g06 0.2 0.8 0.9 0.6 3.5 4.5 6.0 6.5 7.0 in floating ts = gnd i vlogic i vcc temperature (c) v logic uvlo threshold (v) 2.8 2.9 4447 g08 2.7 2.6 2.5 C10 C40 110 20 50 80 rising threshold falling threshold temperature (c) v cc uvlo threshold (v) 3.2 3.3 4447 g09a 3.1 3.0 2.9 C10 C40 110 20 50 80 rising threshold falling threshold temperature (c) uvlo threshold hysteresis (v) 150 250 200 4447 g09b 100 50 0 C10 C40 110 20 50 80 v cc uvlo v logic uvlo
LTC4447 5 4447f typical performance characteristics schottky diode forward voltage vs diode current supply current vs input frequency propagation delay vs v logic supply voltage propagation delay vs v cc supply voltage schottky diode forward voltage vs temperature rise and fall time vs v cc supply voltage switching supply current vs load capacitance rise and fall time vs load capacitance propagation delay vs temperature diode current (ma) 0 0 diode forward voltage (v) 0.1 0.2 0.3 0.4 0.5 0.6 50 100 150 200 4447 g10 temperature (c) schottky diode forward voltage (v) 0.4 0.6 0.5 4447 g11 0.3 0.2 0.1 0 C10 C40 110 20 50 80 i d = 100ma i d = 10ma i d = 1ma frequency (hz) 0 5 6 800k 4447 g12 4 3 200k 400k 600k 1m 2 1 0 supply current (ma) no load v logic = v cc = 5v ts = gnd i vcc i vlogic load capacitance (nf) 0.1 supply current (ma) 1 10 100 4447 g13 31030 v logic = v cc = 5v ts = gnd i cc f in = 500khz i cc f in = 100khz i logic f in = 500khz 1 v cc supply voltage (v) 3.5 15 10 5 0 5.0 6.0 4447 g14 4.0 4.5 5.5 6.5 rise/fall time (ns) c load = 3.3nf ts = gnd t r(tg) t r(bg) t f(tg) t f(bg) load capacitance (nf) 3 1 rise/fall time (ns) 10 100 10 30 4447 g15 v cc = 5v ts = gnd t r(bg) t r(tg) t f(tg) 1 t f(bg) v logic supply voltage (v) 3.5 3.0 25 15 20 10 5 5.0 6.0 4447 g16 4.0 4.5 5.5 6.5 propagation dleay (ns) no load v cc = 5v ts = gnd t phl(tg) t plh(bg) t plh(tg) t phl(bg) v cc supply voltage (v) 20 15 10 5 5.0 6.0 4447 g17 4.0 4.5 5.5 6.5 propagation dleay (ns) no load v logic = 5v ts = gnd t phl(tg) t plh(bg) t plh(tg) t phl(bg) temperature (c) propagation delay (ns) 4447 g18 15 0 C40 C10 20 50 80 110 25 20 10 5 no load v cc = v logic = 5v ts = gnd t phl(tg) t plh(bg) t plh(tg) t phl(bg)
LTC4447 6 4447f block diagram pin functions nc (pins 1, 2): no connection required. tg (pin 3): high side gate driver output (top gate). this pin swings between ts and boost. ts (pin 4): high side mosfet source connection (top source). bg (pin 5): low side gate driver output (bottom gate). this pin swings between v cc and gnd. gnd (pin 6): chip ground. in (pin 7): input signal. input referenced to an internal supply baised off of v logic (pin 8) and gnd (pin 6). if this pin is ? oating, an internal resistive divider triggers a shutdown mode in which both bg (pin 5) and tg (pin 3) are pulled low. trace capacitance on this pin should be minimized to keep the shutdown time low. v logic (pin 8): logic supply. this pin powers the input buffer and logic. connect this pin to the power supply of the controller that is driving in (pin 7) to match input thresholds or to v cc (pin 9) to simplify pcb routing. v cc (pin 9): output driver supply. this pin powers the low side gate driver output directly and the high side gate driver output through an internal schottky diode con- nected between this pin and boost. a low esr ceramic bypass capacitor should be tied between this pin and gnd (pin 6). boost (pins 10, 11, 12): high side bootstrapped supply. an external capacitor should be tied between these pins and ts (pin 4). an internal schottky diode is connected between v cc (pin 9) and these pins. voltage swing at these pins is from v cc C v d to v in + v cc C v d , where v d is the forward voltage drop of the schottky diode. exposed pad (pin 13): ground. the exposed pad must be soldered to pcb ground for optimal electrical and thermal performance. 10 3 4 shoot- through protection three-state input buffer level shifter internal supply undervoltage lockout undervoltage lockout boost 11 12 tg ts 5 8 bg 4447 bd v cc 7k 7k v logic 9 v cc 7 in 6 gnd 13 gnd
LTC4447 7 4447f operation timing diagram figure 1. three-state input operation v il(bg) v il(tg) v il(bg) 90% in tg bg 90% 10% t r(tg) t plh(tg) 10% t r(bg) 4447 td t f(bg) t f(tg) t plh(bg) t phl(bg) t phl(tg) overview the LTC4447 receives a ground-referenced, low voltage digital input signal to drive two n-channel power mosfets in a synchronous power supply con? guration. the gate of the low side mosfet is driven either to v cc or gnd, depending on the state of the input. similarly, the gate of the high side mosfet is driven to either boost or ts by a supply bootstrapped off of the switch node (ts). input stage the LTC4447 employs a unique three-state input stage with transition thresholds that are proportional to the v logic supply. the v logic supply can be tied to the controller ics power supply so that the input thresholds will match those of the controllers output signal. alternatively, v logic can be tied to v cc to simplify routing. an internal voltage regulator in the LTC4447 limits the input threshold values for v logic supply voltages greater than 5v. the relationship between the transition thresholds and the three input states of the LTC4447 is illustrated in figure 1. when the voltage on in is greater than the threshold v ih(tg) , tg is pulled up to boost, turning the high side mosfet on. this mosfet will stay on until in falls below v il(tg) . similarly, when in is less than v ih(bg) , bg is pulled up to v cc , turning the low side (synchronous) mosfet on. bg will stay high until in increases above the threshold v il(bg) . the thresholds are positioned to allow for a region in which both bg and tg are low. an internal resistive divider will pull in into this region if the signal driving the in pin goes into a high impedance state. one application of this three-state input is to keep both of the power mosfets off while an undervoltage condition exists on the controller ic power supply. this can be ac- complished by driving the in pin with a logic buffer that has an enable pin. with the enable pin of the buffer tied to the power good pin of the controller ic, the logic buf- fer output will remain in a high impedance state until the controller con? rms that its supply is not in an undervoltage state. the three-state input of the LTC4447 will therefore pull in into the region where tg and bg are low until the controller has enough voltage to operate predictably. tg high tg high v ih(tg) v il(bg) v il(tg) v ih(bg) in tg low tg low bg low bg high 4447 f01 bg low bg high
LTC4447 8 4447f operation rise/fall time since the power mosfets generally account for the major- ity of power loss in a converter, it is important to quickly turn them on and off, thereby minimizing the transition time and power loss. the LTC4447s peak pull-up current of 3.2a for both bg and tg produces a rapid turn-on transition for the mosfets. this high current is capable of driving a 3nf load with an 8ns risetime. it is also important to turn the power mosfets off quickly to minimize power loss due to transition time; however, an additional bene? t of a strong pull-down on the driver outputs is the prevention of cross-conduction current. for example, when bg turns the low side power mosfet off and tg turns the high side power mosfet on, the volt- age on the ts pin will rise to v in very rapidly. this high frequency positive voltage transient will couple through the c gd capacitance of the low side power mosfet to the bg pin. if the bg pin is not held down suf? ciently, the voltage on the bg pin will rise above the threshold voltage of the low side power mosfet, momentarily turning it back on. as a result, both the high side and low side mosfets will be conducting, which will cause signi? cant cross-conduction current to ? ow through the mosfets from v in to ground, thereby introducing substantial power loss. a similar effect occurs on tg due to the c gs and c gd capacitances of the high side mosfet. the hysteresis between the corresponding v ih and v il voltage levels eliminates false triggering due to noise during switch transitions; however, care should be taken to keep noise from coupling into the in pin, particularly in high frequency, high voltage applications. undervoltage lockout the LTC4447 contains undervoltage lockout detectors that monitor both the v cc and v logic supplies. when v cc falls below 3.04v or v logic falls below 2.65v, the output pins bg and tg are pulled to gnd and ts, respectively. this turns off both of the external mosfets. when v cc and v logic have adequate supply voltage for the LTC4447 to operate reliably, normal operation will resume. adaptive shoot-through protection internal adaptive shoot-through protection circuitry monitors the voltages on the ex ternal mosfets to ensure that they do not conduct simultaneously. the LTC4447 does not allow the bottom mosfet to turn on until the gate-source voltage on the top mosfet is suf? ciently low, and vice-versa. this feature improves ef? ciency by eliminating cross-conduction current from ? owing from the v in supply through the mosfets to ground during a switch transition. output stage a simpli? ed version of the LTC4447s output stage is shown in figure 2. the pull-up device on both the bg and tg outputs is an npn bipolar junction transistor (q1 and q2) in parallel with a low resistance p-channel mosfet (p1 and p2). this powerful combination rapidly pulls the bg and tg outputs to their positive rails (v cc and boost, respectively). both bg and tg have n-channel mosfet pull-down devices (n1 and n2) which pull bg and tg down to their negative rails, gnd and ts. an ad- ditional npn bipolar junction transistor (q3) is present on bg to increase its pull-down drive current capacity. the rail-to-rail voltage swing of the bg and tg output pins is important in driving external power mosfets, whose r ds(on) is inversely proportional to its gate overdrive voltage (v gs C v th ). boost LTC4447 tg ts c gs c gd high side power mosfet v in v cc bg n2 p2 q2 gnd c gs 4447 f02 c gd low side power mosfet load inductor q3 n1 p1 q1 figure 2. capacitance seen by bg and tg during switching
LTC4447 9 4447f applications information operation the LTC4447s powerful parallel combination of the n-channel mosfet (n2) and npn (q3) on the bg pull-down generates a phenomenal 4ns fall time on bg while driving a 3nf load. similarly, the 0.8 pull-down power dissipation to ensure proper operation and long-term reliability, the LTC4447 must not operate beyond its maximum temperature rating. package junction temperature can be calculated by: t j = t a + (p d )( e ja ) where: t j = junction temperature t a = ambient temperature p d = power dissipation e ja = junction-to-ambient thermal resistance power dissipation consists of standby, switching and capacitive load power losses: p d = p dc + p ac + p qg where: p dc = quiescent power loss p ac = internal switching loss at input frequency f in p qg = loss due turning on and off the external mosfet with gate charge q g at frequency f in the LTC4447 consumes very little quiescent current. the dc power loss at v logic = 5v and v cc = 5v is only (730a + 600a)(5v) = 6.65mw. at a particular switching frequency, the internal power loss increases due to both ac currents required to charge and discharge internal nodal capacitances and cross-conduc- tion currents in the internal logic gates. the sum of the quiescent current and internal switching current with no load are shown in the typical performance characteristics plot of switching supply current vs input frequency. the gate charge losses are primarily due to the large ac currents required to charge and discharge the capacitance of the external mosfets during switching. for identical pure capacitive loads c load on tg and bg at switching frequency ? n, the load losses would be: p cload = (c load )(f in )[(v boost C ts ) 2 + (v cc ) 2 ] in a typical synchronous buck con? guration, v boost C ts is equal to v cc C v d , where v d is the forward voltage drop of the internal schottky diode between v cc and boost. if this drop is small relative to v cc , the load losses can be approximated as: p cload 2(c load )(f in )(v cc ) 2 unlike a pure capacitive load, a power mosfets gate capacitance seen by the driver output varies with its v gs voltage level during switching. a mosfets capacitive load power dissipation can be calculated using its gate charge, q g . the q g value corresponding to the mosfets v gs value (v cc in this case) can be readily obtained from the manufacturers q g vs v gs curves. for identical mosfets on tg and bg: p qg 2(v cc )(q g )(f in ) to avoid damaging junction temperatures due to power dissipation, the LTC4447 includes a temperature monitor that will pull bg and tg low if the junction temperature exceeds 160c. normal operation will resume when the junction temperature cools to less than 135c. mosfet (n1) on tg results in a rapid 7ns fall time with a 3nf load. these powerful pull-down devices minimize the power loss associated with mosf e t turn- of f time and cross-conduction current.
LTC4447 10 4447f applications information typical application bypassing and grounding the LTC4447 requires proper bypassing on the v logic , v cc and v boost C ts supplies due to its high speed switching (nanoseconds) and large ac currents (amperes). careless component placement and pcb trace routing may cause excessive ringing and under/overshoot. to obtain the optimum performance from the LTC4447: ? mount the bypass capacitors as close as possible between the v logic and gnd pins, the v cc and gnd pins, and the boost and ts pins. the leads should be shortened as much as possible to reduce lead inductance. ? use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. remember that the LTC4447 switches greater than 5a peak currents and any signi? cant ground drop will degrade signal integrity. ? plan the power/ground routing carefully. know where the large load switching current is coming from and going to. maintain separate ground return paths for the input pin and the output power stage. ? keep the copper trace between the driver output pin and the load short and wide. ? be sure to solder the exposed pad on the back side of the LTC4447 packages to the board. correctly soldered to a double-sided copper board, the LTC4447 has a thermal resistance of approximately 43c/w. failure to make good thermal contact between the exposed back side and the copper board will result in thermal resistances far greater. tg boost c5 0.22f m1 rjk0305 2 m2 rjk0301 2 v out 330f 6 4447 ta02 l1 0.3h r3 c6 gnd ts v logic v cc LTC4447 bg in c4 c3 1f r2 + c2 c1 1k r sense r cm d1 r1 load rtn v 12sen sdata sclk smb_al_n pwrgd outen sync_in sync_out fault1 fault2 i out/ish i sh_gnd v cc pmbus interface v d33 v d25 12v 5v gnd ltc7510 pwm tempsen reset_n i senn i senp v senp v senn saddr v set fset v trim i maxset 1k 1k 1k 1k power management interface multiphase interface fault outputs i-share + ltc7510/LTC4447 12v to 1.5v/30a digital step-down dc/dc converter with pmbus serial interface
LTC4447 11 4447f information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . package description ddma package 12-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1743 rev a) 3.00 0.10 3.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad and tie bars shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.11 0.05 0.40 0.10 0.81 0.10 0.63 0.05 bottom viewexposed pad 1.35 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 1 6 12 7 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd12ma) dfn 0507 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.23 0.05 0.25 0.05 2.25 ref 2.38 0.05 1.35 0.05 0.81 0.05 0.57 0.05 1.07 0.05 1.19 0.05 0.93 0.05 0.70 0.05 2.10 0.05 3.50 0.05 package outline pin 1 notch r = 0.20 or 0.25 45 chamfer 2.38 0.10 2.25 ref 0.45 bsc 0.45 bsc
LTC4447 12 4447f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0608 ? printed in usa related parts part number description comments ltc1154 high side micropower mosfet driver internal charge pump 4.5v to 18v supply range ltc1155 dual micropower high/low side driver internal charge pump 4.5v to 18v supply range lt ? 1161 quad protected high side mosfet driver 8v to 48v supply range, t on = 200s, t off = 28s ltc1163 triple 1.8v to 6v high side mosfet driver 1.8v to 6v supply range, t on = 95s, t off = 45s ltc1693 family high speed single/dual n-channel mosfet drivers 1.5a peak output current, 4.5v v in 13.2v ltc3900 synchronous recti? er driver for forward converters pulse drive transformer synchronous input ltc3901 secondary side synchronous driver for push-pull and full-bridge converters gate drive transformer synchronous input ltc4440 high speed, high voltage high side gate driver high side source up to 100v, 8v v cc 15v ltc4440-5 high speed, high voltage high side gate driver high side source up to 80v, 4v v cc 15v ltc4441 6a mosfet driver 6a peak output current, adjustable gate drive from 5v to 8v, 5v v in 25v ltc4442/ltc4442-1 high speed synchronous n-channel mosfet driver 5a peak output current, three-state input, 38v maximum input supply voltage, 6v v cc 9.5v, ms8e package ltc4443/ltc4443-1 high speed synchronous n-channel mosfet driver 5a peak output current, internal schottky diode, 38v maximum input supply voltage, 6v v cc 9.5v, 3mm 3mm dfn-12 ltc4444/ltc4444-5 high voltage/high speed synchronous n-channel mosfet driver 3a peak output current, 100v maximum input supply voltage, 4.5v v cc 13.5v, with adaptive shoot through protection ltc4446 high voltage high side/low side n-channel mosfet driver 3a output current, 100v input supply voltage, 7.2v v cc 13.5v, without adaptive shoot through protection ltc7510 digital dc/dc controller with pmbus interface digital controller, pmbus serial interface, 150khz to 2mhz switching frequency

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